A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs
Identifieur interne : 001194 ( Main/Repository ); précédent : 001193; suivant : 001195A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs
Auteurs : RBID : Pascal:13-0363075Descripteurs français
- Pascal (Inist)
- Endommagement, Technologie silicium sur isolant, Transistor MOSFET, Technologie MOS, Nanoélectronique, Tension drain, Tension amorçage, Tension disruptive, Circuit à transistor unique, Circuit de verrouillage, Barrière potentiel, Bande valence, Drain, Technologie bipolaire, Evaluation performance, Fiabilité, Circuit VLSI, VLSI, Silicium, Arséniure d'indium, Corps flottant, Couche ultramince, Semiconducteur bande interdite étroite, 8530T, 8535, 8540L.
English descriptors
- KwdEn :
- Bipolar technology, Breakdown voltage, Damaging, Disruptive voltage, Drain, Drain voltage, Floating body, Indium arsenides, Latch circuit, MOS technology, MOSFET, Nanoelectronics, Narrow band gap semiconductors, Performance evaluation, Potential barrier, Reliability, Silicon, Silicon on insulator technology, Single transistor circuit, Ultrathin films, VLSI, VLSI circuit, Valence band.
Abstract
We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.
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<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" level="a">A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs</title><author><name sortKey="Abbasi, Abdollah" uniqKey="Abbasi A">Abdollah Abbasi</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Electrical Engineering Department, Semnan University</s1><s2>Semnan</s2><s3>IRN</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ></inist:fA14><country>Iran</country><wicri:noRegion>Semnan</wicri:noRegion></affiliation></author><author><name sortKey="Orouji, Ali A" uniqKey="Orouji A">Ali A. Orouji</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Electrical Engineering Department, Semnan University</s1><s2>Semnan</s2><s3>IRN</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ></inist:fA14><country>Iran</country><wicri:noRegion>Semnan</wicri:noRegion></affiliation></author></titleStmt><publicationStmt><idno type="inist">13-0363075</idno><date when="2013">2013</date><idno type="stanalyst">PASCAL 13-0363075 INIST</idno><idno type="RBID">Pascal:13-0363075</idno><idno type="wicri:Area/Main/Corpus">000434</idno><idno type="wicri:Area/Main/Repository">001194</idno></publicationStmt><seriesStmt><idno type="ISSN">1369-8001</idno><title level="j" type="abbreviated">Mater. sci. semicond. process.</title><title level="j" type="main">Materials science in semiconductor processing</title></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Bipolar technology</term><term>Breakdown voltage</term><term>Damaging</term><term>Disruptive voltage</term><term>Drain</term><term>Drain voltage</term><term>Floating body</term><term>Indium arsenides</term><term>Latch circuit</term><term>MOS technology</term><term>MOSFET</term><term>Nanoelectronics</term><term>Narrow band gap semiconductors</term><term>Performance evaluation</term><term>Potential barrier</term><term>Reliability</term><term>Silicon</term><term>Silicon on insulator technology</term><term>Single transistor circuit</term><term>Ultrathin films</term><term>VLSI</term><term>VLSI circuit</term><term>Valence band</term></keywords><keywords scheme="Pascal" xml:lang="fr"><term>Endommagement</term><term>Technologie silicium sur isolant</term><term>Transistor MOSFET</term><term>Technologie MOS</term><term>Nanoélectronique</term><term>Tension drain</term><term>Tension amorçage</term><term>Tension disruptive</term><term>Circuit à transistor unique</term><term>Circuit de verrouillage</term><term>Barrière potentiel</term><term>Bande valence</term><term>Drain</term><term>Technologie bipolaire</term><term>Evaluation performance</term><term>Fiabilité</term><term>Circuit VLSI</term><term>VLSI</term><term>Silicium</term><term>Arséniure d'indium</term><term>Corps flottant</term><term>Couche ultramince</term><term>Semiconducteur bande interdite étroite</term><term>8530T</term><term>8535</term><term>8540L</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.</div></front></TEI><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>1369-8001</s0></fA01><fA03 i2="1"><s0>Mater. sci. semicond. process.</s0></fA03><fA05><s2>16</s2></fA05><fA06><s2>6</s2></fA06><fA08 i1="01" i2="1" l="ENG"><s1>A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs</s1></fA08><fA11 i1="01" i2="1"><s1>ABBASI (Abdollah)</s1></fA11><fA11 i1="02" i2="1"><s1>OROUJI (Ali A.)</s1></fA11><fA14 i1="01"><s1>Electrical Engineering Department, Semnan University</s1><s2>Semnan</s2><s3>IRN</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ></fA14><fA20><s1>1821-1827</s1></fA20><fA21><s1>2013</s1></fA21><fA23 i1="01"><s0>ENG</s0></fA23><fA43 i1="01"><s1>INIST</s1><s2>2888A</s2><s5>354000501052880740</s5></fA43><fA44><s0>0000</s0><s1>© 2013 INIST-CNRS. All rights reserved.</s1></fA44><fA45><s0>24 ref.</s0></fA45><fA47 i1="01" i2="1"><s0>13-0363075</s0></fA47><fA60><s1>P</s1></fA60><fA61><s0>A</s0></fA61><fA64 i1="01" i2="1"><s0>Materials science in semiconductor processing</s0></fA64><fA66 i1="01"><s0>GBR</s0></fA66><fC01 i1="01" l="ENG"><s0>We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.</s0></fC01><fC02 i1="01" i2="X"><s0>001D11G05</s0></fC02><fC02 i1="02" i2="X"><s0>001D03F04</s0></fC02><fC02 i1="03" i2="X"><s0>001D03F18</s0></fC02><fC02 i1="04" i2="X"><s0>001D03F06A</s0></fC02><fC02 i1="05" i2="X"><s0>240</s0></fC02><fC03 i1="01" i2="X" l="FRE"><s0>Endommagement</s0><s5>01</s5></fC03><fC03 i1="01" i2="X" l="ENG"><s0>Damaging</s0><s5>01</s5></fC03><fC03 i1="01" i2="X" l="SPA"><s0>Deterioración</s0><s5>01</s5></fC03><fC03 i1="02" i2="X" l="FRE"><s0>Technologie silicium sur isolant</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="ENG"><s0>Silicon on insulator technology</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="SPA"><s0>Tecnología silicio sobre aislante</s0><s5>02</s5></fC03><fC03 i1="03" i2="3" l="FRE"><s0>Transistor MOSFET</s0><s5>03</s5></fC03><fC03 i1="03" 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